In many state of the art integrated circuits, emphasis is placed on providing signal amplification with low noise and low power dissipation. There are always demands for circuit improvements that enable higher functional throughput, increased on-chip signal processing, higher data rates, lower noise, less power dissipation, smaller cell size, and greater radiation hardness. In general, improved unit cell designs are needed to maximize functionality and provide high gain while minimizing noise, power dissipation, and cell size. Unfortunately, increased unit cell functionality usually requires greater circuit complexity, which leads to more noise and increased power dissipation. These conflicting requirements stretch the capabilities of many of the present electronic circuit designs.
In the electronic circuitry of focal plane array (FPA) detectors, for example, the input cells that integrate the photocurrent generated in the detectors have two conflicting requirements. During the time when integration occurs, the input capacitance of the detector and input cell must be sufficiently large to minimize debiasing of the detector. During readout of the detector, however, the input capacitance should be very small to maximize the output voltage that is a measure of the integrated current. Prior circuit designs have attempted to compromise these conflicting requirements, with the result of allowing some nonlinearities from detector debiasing while accepting low output voltage with a usable signal-to-noise ratio.
Specifications for advanced FPAs require sensing of very low signal levels. For a detector system to maintain good sensitivity and resolution, the readout device of the FPA must amplify input signals received at the noise equivalent input (NEI) photon level so that the output signals are above the noise floor of the multiplexer and data processing electronics that follow the FPA. In some FPA applications, the sensor is required to perform in a low flux background while covering a wide dynamic range. The input cell design for the readout device in such a sensor is limited to either a capacitive transimpedance amplifier (CTIA) or a direct integration approach. A standard switched FET multiplexer design (source follower per cell), for example, ignores the need for amplification, with the result that the output voltage tracts the input node voltage with near unity gain. The advantage of this design is circuit simplicity and threshold voltage variation tolerance.
In state-of-the-art sensors, a detector bias change limitation is required for either 1/f noise suppression (in mercury cadmium telluride detectors) or response linearity maintenance (in impurity band conduction (IBC) detectors). For IBC detectors, the input and output node voltage swings are limited to 0.4 volts or less to maintain good detector response linearity. As a result, an amplifier is usually added to the standard switched FET multiplexer described above. The added amplifier, however, significantly increases cell size and complexity as well as power dissipation. The amplifier also tends to behave as an additional noise source. Thus, the amplifier, which is added to improve the noise performance of the multiplexer, is somewhat self-defeating in that it contributes to the noise of the circuit.
FIG. 1 illustrates a prior art FPA output device comprising a conventional amplifier 11 added to a standard switched FET multiplexer 12 as described above. Amplifier 11 contains FETs 13, 14, and 15 and capacitor 16 configured to amplify the signal on input node 18 to an acceptable value on output node 19. This design solves the detector debiasing problem, but it requires a relatively large amount of space in an integrated circuit and it consumes power in proportion to the speed at which it operates. Because of these deficiencies, there is a need for an improved readout circuit that provides higher functional throughput, increased on-chip signal processing, higher data rates, more pixels per array, lower noise, less power dissipation, smaller cell size, and greater radiation hardness.